Figure 1 shows
a block diagram of the Pentium
design.
The most important enhancements
over the 486 are the separate
instruction and data caches,
the dual integer pipelines (the
U-pipeline and the V-pipeline,
as Intel calls them), branch
prediction using the branch
target buffer (BTB), the pipelined
floating-point unit, and the
64-bit external data bus. Even-parity
checking is implemented for
the data bus and the internal
RAM arrays (caches and TLBs).
As for new functions, there
are only a few; nearly all the
enhancements in Pentium are
included to improve performance,
and there are only a handful
of new instructions. Pentium
is the first high-performance
micro-processor to include a
system management mode like
those found on power-miserly
processors for notebooks and
other battery-based applications;
Intel is holding to its promise
to include SMM on all new CPUs.
Pentium uses about 3 million
transistors on a huge 294 mm
2 (456k mils 2 ). The caches
plus TLBs use only about 30%
of the die. At about 17 mm on
a side, Pentium is one of the
largest microprocessors ever
fabricated and probably pushes
Intel’s production equipment
to its limits. The integer data
path is in the middle, while
the floating-point data path
is on the side opposite the
data cache. In contrast to other
superscalar designs, such as
SuperSPARC, Pentium’s
integer data path is actually
bigger than its FP data path.
This is an indication of the
extra logic associated with
complex instruction support.
Intel estimates about 30% of
the transistors were devoted
to compatibility with the x86
architecture. Much of this overhead
is probably in the microcode
ROM, instruction decode and
control unit, and the adders
in the two address generators,
but there are other effects
of the complex instruction set.
For example, the higher frequency
of memory references in x86
programs compared to RISC code
led to the implementation of
the dual-ac.
Register set
The purpose of the Register
is to hold temporary results,
and control the execution of
the program. General-purpose
registers in Pentium are EAX,
ECX, EDX, EBX, ESP, EBP,ESI,
or EDI.
The 32-bit registers are named
with prefix E, EAX, etc, and
the least 16 bits 0-15 of these
registers can be accessed with
names such as AX, SI Similarly
the lower eight bits (0-7) can
be accessed with names such
as AL & BL. The higher eight
bits (8-15) with names such
as AH & BH. The instruction
pointer EAP known as program
counter(PC) in 8-bit microprocessor,
is a 32-bit register to handle
32-bit memory addresses, and
the lower 16 bit segment IP
is used for 16-bi memory address.
The flag register is a 32-bit
register , however 14-bits are
being used at present for 13
different tasks; these flags
are upward compatible with those
of the 8086 and 80286. The comparison
of the available flags in 16-bit
and 32-bit microprocessor is
may provide some clues related
to capabilities of these processors.
The 8086 has 9 flags, the 80286
has 11 flags, and the 80286
has 13 flags. All of these flag
registers include 6 flags related
to data conditions (sign, zero,
carry, auxiliary, carry , overflow,
and parity) and three flags
related to machine operations.(interrupts,
Single-step and Strings). The
80286 has two additional : I/O
Privilege and Nested Task. The
I/O Privilege uses two bits
in protected mode to determine
which I/O instructions can be
used, and the nested task is
used to show a link between
two tasks.
The processor also includes
control registers and system
address registers , debug and
test registers for system and
debugging operations.
Addressing mode & Types
of instructions
Instruction set is divided
into 9 categories of operations
and has 11 addressing modes.
In addition to commonly available
instructions in a 8 bit microprocessor
and this set includes operations
such as bit manipulation and
string operations, high level
language support and operating
system support. An instruction
may have 0-3 operands and the
operand can be 8, 16, or 32-
bits long. The 80386 handles
various types of data such as
Single bit , string of bits
, signed and unsigned 8-, 16-,
32- and 64- bit data, ASCII
character and BCD numbers.
High level language support
group includes instructions
such as ENTER and LEAVE. The
ENTER instruction is used to
ENTER from a high level language
and it assigns memory location
on the stack for the routine
being entered and manages the
stack. On the other hand the
LEAVE generates a return procedure
for a high level language. The
operating system support group
includes several instructions
, such as APRL.( Adjust Requested
Privilege Level) and the VERR/W
(Verify Segment for Reading
or Writing). The APRL is designed
to prevent the operating system
from gaining access to routines
with a higher priority level
and the instructions VERR/W
verify whether the specified
memory address can be reached
from the current privilege level.
Cont...... |
